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2.4G+5G
Without BT
1T1R
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PCIe Interface
H256NN-S SV6256P
H256NN-S is a low-power module with the highest level of integration for internet of thing embedded systems. It is designed to support all mandatory IEEE 802.11b data rates of 1, 2, 5.5 and 11 Mbps, all 802.11g payload data rates of 6, 9, 12, 18, 24, 36, 48 and 54 Mbps, as well as 802.11n MCS0~MCS7, HT20/HT40, 800ns and 400ns guard interval. The Main chip WLAN is designed to support IEEE 802.11 a/b/g/n single stream with the state of-the-art design techniques and process technology to achieve low power consumption and high throughput performance to address the requirement of mobile and handheld devices.
The Main chip WLAN low power function uses the innovative design techniques and the optimized architecture which best utilizes the advanced process technology to reduce active and idle power, and achieve extreme low power consumption at sleep state to extend the battery life. The Main chip WLAN A-MPDU Tx function maximizes the throughput performance while achieving the best buffer utilization.
General Features
support IEEE 802.11 a/b/g/n single stream
Single stream 802.11n provides highest throughput and superior RF performance for embedded system
Integrated dual-band WLAN CMOS efficient power amplifier with internal power detector and closed loop power calibration
Enhanced and robust sensitivity for wider coverage range
Host Interface
Supports popular interfaces: SDIO 2.0 (50MHz, 4-bit and 1-bit) / SPI
Ordering Information
H256NN-S SV6256P
H256NN-S is a low-power module with the highest level of integration for internet of thing embedded systems. It is designed to support all mandatory IEEE 802.11b data rates of 1, 2, 5.5 and 11 Mbps, all 802.11g payload data rates of 6, 9, 12, 18, 24, 36, 48 and 54 Mbps, as well as 802.11n MCS0~MCS7, HT20/HT40, 800ns and 400ns guard interval. The Main chip WLAN is designed to support IEEE 802.11 a/b/g/n single stream with the state of-the-art design techniques and process technology to achieve low power consumption and high throughput performance to address the requirement of mobile and handheld devices.
The Main chip WLAN low power function uses the innovative design techniques and the optimized architecture which best utilizes the advanced process technology to reduce active and idle power, and achieve extreme low power consumption at sleep state to extend the battery life. The Main chip WLAN A-MPDU Tx function maximizes the throughput performance while achieving the best buffer utilization.
General Features
support IEEE 802.11 a/b/g/n single stream
Single stream 802.11n provides highest throughput and superior RF performance for embedded system
Integrated dual-band WLAN CMOS efficient power amplifier with internal power detector and closed loop power calibration
Enhanced and robust sensitivity for wider coverage range
Host Interface
Supports popular interfaces: SDIO 2.0 (50MHz, 4-bit and 1-bit) / SPI
Ordering Information
